The present invention relates to a protection element of a semiconductor device formed on a semiconductor substrate and a fabrication method for such a protection element.
Japanese Laid-Open Patent Publication No. 59-125654 describes a technology in which in a conventional semiconductor memory device including a MOS capacitor and a field effect transistor as an information memory unit (memory cell), a MOS capacitor having an insulating film of which breakdown voltage is relatively low compared with that of the MOS capacitor of the memory cell is used as a protection element.
FIG. 7 is a cross-sectional view of the protection element of the semiconductor memory device described in the above patent publication. As shown in FIG. 7, a field effect transistor includes impurity diffusion layers 102 and 103 serving as the source/drain, and a second conductive layer 106 serving as the gate located above the impurity diffusion layers via a gate insulating film 107 made of a silicon dioxide film.
A MOS capacitor (I) in a memory cell is composed of the impurity diffusion layer 103 and a first conductive layer 105 with a dielectric layer 108 made of a silicon dioxide film interposed therebetween. A MOS capacitor (II) as the protection element is composed of the first conductive layer 105 and a reversal layer 110 with a silicon dioxide layer 109 thinner than the silicon dioxide layer of the MOS capacitor (I) in the memory cell interposed therebetween.
Once charge is induced in the first conductive layer 105, breakdown predominantly occurs in the MOS capacitor (II) as the protection element that is lower in breakdown voltage than the MOS capacitor (I) in the memory cell, causing the charge in the first conductive layer 105 to flow into a semiconductor substrate 101 via the MOS capacitor (II) as the protection element, preventing occurrence of further charging up. The MOS capacitor (I) in the memory cell is therefore protected.